This application is related to the following co-pending, commonly assigned U.S. patent applications: entitled xe2x80x9cStatic Pass Transistor Logic with Transistors with Multiple Vertical Gates,xe2x80x9d Ser. No. 09/580,901; and xe2x80x9cVertical Gate Transistors in Pass Transistor Logic Decode Circuits,xe2x80x9d Ser. No. 09/580,860, now U.S. Pat. No. 6,222,788, both filed on May 30, 2000 and which disclosures are herein incorporated by reference.
This invention relates generally to integrated circuits and in particular to vertical gate transistors in pass transistor programmable logic arrays.
Many programmable logic arrays include multiple transistors arrayed such that a combination of activated transistors produce a logical function. Such transistors in the array are activated, in the case of MOSFET devices, by either applying or not applying a potential to the gate of the MOSFET. This action either turns on the transistor or turns off the transistor. Conventionally, each logical input to the programmable logic array is applied to an independent MOSFET gate. Thus, according to the prior art, a full MOSFET is required for each input to the programmable logic array. Requiring a full MOSFET for each logic input consumes a significant amount of chip surface area. Conventionally, the size of each full MOSFET, e.g. the space it occupies, is determined by the minimum lithographic feature dimension. Thus, the number of logical functions that can be performed by a given programmable logic array is dependent upon the number of logical inputs which is dependent upon the available space to in which to fabricate an independent MOSFET for each logic input. In other words, the minimum lithographic feature size and available surface determine the functionality limits of the programmable logic array.
Pass transistor logic is one of the oldest logic techniques and has been described and used in NMOS technology long before the advent of the CMOS technology currently employed in integrated circuits. A representative textbook by L. A. Glasser and D. W. Dobberpuhl, entitled xe2x80x9cThe design and analysis of VLSI circuits,xe2x80x9d Addison-Wesley, Reading Mass., 1985, pp. 16-20, describes the same. Pass transistor logic was later described for use in complementary pass transistor circuits in CMOS technology. Items which outline such use include a textbook by J. M. Rabaey, entitled xe2x80x9cDigital Integrated Circuits; A design perspective,xe2x80x9d Prentice Hall, Upper Saddle River, N.J., pp. 210-222, 1996, and an article by K. Bernstein et al., entitled xe2x80x9cHigh-speed design styles leverage IBM technology prowess,xe2x80x9d MicroNews, vol. 4, no. 3, 1998. What more, there have been a number of recent applications of complementary pass transistor logic in microprocessors. Articles which describe such applications include articles by T. Fuse et al., entitled xe2x80x9cA 0.5 V 200 mhz 1-stage 32b ALU using body bias controlled SOI pass-gate logic,xe2x80x9d Dig. IEEE Int. Solid-State Circuits Conf., San Francisco, pp. 286-287, 1997, an article by K. Yano et al., entitled xe2x80x9cTop-down pass-transistor logic design,xe2x80x9d IEEE J. Solid-State Circuits, Vol. 31, no. 6, pp. 792-803, June 1996, and an article by K. H. Cheng et al., entitled xe2x80x9cA 1.2 V CMOS multiplier using low-power current-sensing complementary pass-transistor logicxe2x80x9d, Proc. Third Int. Conf. On Electronics, Circuits and Systems, Rodos, Greece, 13-16 October, vol. 2, pp. 1037-40, 1996.
In another approach, differential pass transistor logic has been developed to overcome concerns about low noise margins in pass transistor logic. This has been described in an article by S. I. Kayed et al., entitled xe2x80x9cCMOS differential pass-transistor logic (CMOS DPTL) predischarge buffer design,xe2x80x9d 13th National Radio Science Conf, Cairo, Egypt, pp. 527-34, 1996, as well as in an article by V. G. Oklobdzija, entitled xe2x80x9cDifferential and pass-transistor CMOS logic for high performance systems,xe2x80x9d Microelectronic J., vol. 29, no. 10, pp. 679-688, 1998. Combinations of pass-transistor and CMOS logic have also been described. S. Yamashita et al., xe2x80x9cPass-transistor? CMOS collaborated logic: the best of both worlds,xe2x80x9d Dig. Symp. On VLSI Circuits, Kyoto, Japan, 12-14 June, pp. 31-32, 1997. Also, a number of comparisons of pass transistor logic and standard CMOS logic have been made for a variety of different applications and power supply voltages. These studies are described in an article by R. Zimmerman et al., entitled xe2x80x9cLow-power logic styles: CMOS versus pass transistor logic,xe2x80x9d IEEE J. Solid-State Circuits, vol. 32, no. 7, pp. 1079-1790, July 1997, and in an article by C. Tretz et al., xe2x80x9cPerformance comparison of differential static CMOS circuit topologies in SOI technology,xe2x80x9d Proc. IEEE Int. SOI Conference, October 5-8, FL, pp. 123-4, 1998.
However, all of these studies and articles on pass transistor logic have not provided a solution to the constraints placed on programmable logic arrays by the limits of the minimum lithographic feature size and the deficit in the available chip surface space. An approach which touches upon overcoming the limits of the minimum lithographic feature size and the deficit in the available chip surface space, is disclosed in the following co-pending, commonly assigned U.S. patent applications by Len Forbes and Kie Y. Ahn, entitled: xe2x80x9cProgrammable Logic Arrays with Transistors with Vertical Gates,xe2x80x9d attorney docket no. 303.683US1, Ser. No. 09/583,584, xe2x80x9cHorizontal Memory Devices with Vertical Gates,xe2x80x9d attorney docket no. 303.691US1, Ser. No. 09/584,566, and xe2x80x9cProgrammable Memory Decode Circuits with Vertical Gates,xe2x80x9d attorney docket no. 303.692US1, Ser. No. 09/584,564. Those disclosures are all directed toward a non volatile memory cell structure having vertical floating gates and vertical control gates above a horizontal enhancement mode channel region. In those disclosures one or more of the vertical floating gates is charged by the application of potentials to an adjacent vertical gate. The devices of those disclosures can be used as flash memory, EAPROM, EEPROM devices, programmable memory address and decode circuits, and/or programmable logic arrays. Those applications, however, are not framed to address overcoming the limits of the minimum lithographic feature size and the deficit in the available chip surface space for purposes of pass transistor logic in programmable logic arrays.
Therefore, there is a need in the art to provide improved pass transistor logic in programmable logic arrays which overcome the aforementioned barriers.
The above mentioned problems with pass transistor logic in programmable logic arrays and other problems are addressed by the present invention and will be understood by reading and studying the following specification. Systems and methods are provided for pass transistor logic in programmable logic arrays having transistors with multiple vertical gates. The multiple vertical gates serve as multiple logic inputs. The multiple vertical gates are edge defined such that only a single transistor is required for multiple logic inputs. Thus, a minimal surface area is required for each logic input.
In one embodiment of the present invention, a novel programmable logic array is provided. The novel programmable logic array includes a plurality of input lines for receiving an input signal, a plurality of output lines, and one or more arrays having a first logic plane and a second logic plane connected between the input lines and the output lines. The first logic plane and the second logic plane comprise a plurality of logic cells arranged in rows and columns for providing a sum-of-products term on the output lines responsive to the received input signal. According to the teachings of the present invention, each logic cell includes a source region and a drain region in a horizontal substrate. A depletion mode channel region separates the source and the drain regions. A number of vertical gates are located above different portions of the depletion mode channel region. At least one of the vertical gates is located above a first portion of the depletion mode channel region and is separated from the channel region by a first thickness insulator material. At least one of the vertical gates is located above a second portion of the channel region and is separated from the channel region by a second thickness insulator material. According to the present invention, there is no source nor drain region associated with each input and the gates have sub-lithographic horizontal dimensions by virtue of being edge defined vertical gates.
These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.